1. Field of the Invention
The invention relates generally to semiconductor devices and manufacturing methods thereof and, more particularly, to semiconductor devices in which a lifetime against electromigration of a conductive metal interconnection including an electric interconnecting portion may be increased and manufacturing methods thereof.
2. Description of the Background Art
Generally, thin aluminum film is largely used as an electrode interconnection material of a semiconductor device represented by an integrated circuit using silicon. With the advancement of miniaturization in semiconductor devices, a multilayer interconnection has been often used for interconnection between electrodes. In the multilayer interconnection, an aluminum film is formed on an impurity diffusion layer or a conductive layer such as a polysilicon layer over the surface of a silicon substrate with an insulating film interposed therebetween by a CVD method or a sputtering method, and the aluminum thin film and the conductive layer underlying it are electrically connected to each other through a contact hole formed in the insulating film.
A description will now be provided of a structure of a conventional semiconductor device having an interconnection structure including an electric connecting portion, and manufacturing processes thereof, referring to FIGS. 1, 2, 3A to 3D.
FIG. 1 shows an example of a typical cross-sectional structure of a conventional bipolar transistor. The bipolar transistor shown in the figure has an n-type layer 3 having a high concentration formed in part of a p-type region 2 on the surface of an n-type semiconductor substrate 1. The p-type region 2 and the high concentration n-type layer 3 are electrically connected to aluminum interconnections 5, 6 through contact holes formed in predetermined positions of an oxide insulating film formed on the surface of the semiconductor substrate 1, respectively. The aluminum interconnections 5, 6 and a conductive layer 7 on the reverse surface of the semiconductor substrate 1 are connected to a base terminal (B), an emitter terminal (E), and a collector terminal (C) of the bipolar transistor, respectively. The aluminum interconnections 5, 6 having such a structure of the semiconductor device are directly in contact with the amorphous oxide insulating film 4 in most part of their under surfaces.
FIG. 2 shows a typical cross-sectional structure of a conventional MOS (Metal Oxide Semiconductor) type field-effect transistor. The MOS type field-effect transistor has a gate electrode 13 and source/drain regions 14 doped with impurities formed on an active region isolated and insulated by a field insulating film 12 on the surface of a semiconductor substrate 11. The source/drain regions 14 are electrically connected to aluminum interconnection layer 17 through contact holes 16 formed in an oxide insulating film 15. In this structure as well, the aluminum interconnection layer 17, over most of its under surface, is in contact with the oxide insulating film 15 having an amorphous structure and it is in contact with the semiconductor substrate 11 having a crystalline structure such as single crystal silicon only in its contact portion with the source/drain regions 14.
A description will now be provide of a process of forming an interconnection on a semiconductor substrate represented by the aluminum interconnections 5, 6 and the like of the planar type bipolar transistor shown in FIG. 1, referring to FIGS. 3A to 3D.
Firstly, an oxide insulating film 22 such as SiO.sub.2 is deposited on a semiconductor substrate 21 by a CVD method or the like (see FIG. 3A). After that, a contact hole 23 is apertured in a predetermined position of the oxide insulating film 22 by a photolithography and etching (see FIG. 3B). Then, an aluminum thin film 24 is formed on the surface of the oxide insulating film 22 including the inner surface of the contact hole 23 by the CVD method or the sputtering method or the like (see FIG. 3C). After that, the aluminum thin film 24 is selectively removed and an aluminum interconnection layer 25 is patterned by the photolithography and etching (see FIG. 3D).
In the above-mentioned process, in forming the aluminum thin film 24, most of the underlying portion thereof is formed on the oxide insulating film 22 having an amorphous structure, so that the aluminum thin film 24 formed has an amorphous structure or a polycrystalline structure in which small crystal grains are formed having a diameter of about 1 .mu.m or below under the influence of the underlying portion. Therefore, there is a problem that the amorphous characteristic results in degradation of the aluminum interconnection layer 25 due to electromigration.
The electromigration is a phenomenon in which when a current flows through the aluminum interconnection layer, migrating free electrons collide with aluminum atoms, so that the aluminum atoms flow particularly along the grain boundary in the direction of the migration of the electrons. A cavity formed after the aluminum atoms leave is expanded by the electromigration, the aluminum interconnection layer becomes thin and its resistance becomes large, or it is electrically disconnected. Therefore, the lifetime of the semiconductor device against electromigration becomes shortened. The electromigration also causes the aluminum atoms which migrated along the grain boundary to accrete in some places, generating a hillock which is an unnecessary lump, so that a defect such as a short-circuit is sometimes caused between adjacent aluminum interconnections in the vicinity.
A conventional technique for solving the abovementioned problem of the electromigration is disclosed, for example, in Japanese Patent Laying-Open No. 64-37050, in which an aluminum interconnection layer 33 is changed to be a single crystal by interposing a single crystal silicon layer 34 as an underlying portion of the aluminum interconnection layer 33 to be formed on an oxide insulating film 32 over a semiconductor substrate 31 as shown in FIG. 4. In the structure shown in FIG. 4, a single crystal CoSi.sub.2 film 36 is formed for reducing the resistance of a contact portion in the vicinity of a region in which at least the single crystal silicon layer 34 is in contact with the surface of the semiconductor substrate 31 through a contact hole 35. In the Japanese Patent Laying-Open No. 64-37050, a MOS type field-effect transistor shown in FIG. 5 is disclosed as one example of application of this technique. The MOS type field-effect transistor is different from that shown in FIG. 2 in that a single crystal aluminum interconnection layer 39 is formed over the oxide insulating film 15 including on the inner peripheral wall and on a bottom surface of a contact hole 38 with a single crystal silicon layer 37 interposed therebetween, and furthermore, a single crystal CoSi.sub.2 film 40 for reducing the contact resistance is formed on the surface of the source/drain regions 14. Other structures are the same as those shown in FIG. 2, so that the description thereof will not be repeated while giving them the same reference numerals.
"JAPANESE JOURNAL OF APPLIED PHYSICS, VOL. 27, NO. 9, SEPTEMBER, 1988, at pp. L1775-L1777" explains the fact that a single crystal aluminum layer can be formed on a single crystal silicon layer, as disclosed in the above-mentioned publication and the like.
In accordance with the conventional technique described in the above-mentioned publication and like references, in the structures shown in FIGS. 4 and 5 a problem is that the single crystal silicon layers 34, 37 which are formed as underlying portions of the aluminum interconnection layers 33, 39 are also formed on the bottom surfaces of the contact holes 35, 38, so that the contact resistances in these portions are increased. This is because the sheet resistance values of the single crystal silicon layers 34, 37 are much larger than the sheet resistance value of the aluminum thin film.